Art

J-GLOBAL ID：201102258057294270   Reference number：11A1329153

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

マイクロプロセッサの機能ユニット上への微粒パワーゲートの設計と実装

Author (8)： LEI Zhao (Keio Univ.) ,  LEI Zhao (Graduate School of Information Systems, Univ. of Electro-Communications) ,  IKEBUCHI Daisuke (Keio Univ.) ,  USAMI Kimiyoshi (Shibaura Inst. of Technol.) ,  NAMIKI Mitaro (Tokyo Univ. of Agriculture and Technol.) ,  KONDO Masaaki (Graduate School of Information Systems, Univ. of Electro-Communications) ,  NAKAMURA Hiroshi (The Univ. of Tokyo) ,  AMANO Hideharu (Keio Univ.)
Material： IPSJ Transactions on System LSI Design Methodology (Web)  (情報処理学会論文誌トランザクション System LSI Design Methodology(Web))
Volume： 4  Page： 182-192 (J-STAGE)  Publication year： 2011 
JST Material Number： U0110A  ISSN： 1882-6687  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *microprocessor ,  *leakage current ,  *electric power control ,  *circuit design ,  *gate(semiconductor)
Semi thesaurus term： leakage current

JST classification (2)： Digital computer hardwares in general  (JC04010C) ,  CAD,CAM  (JE10000A)

Reference (22)：

• 1) Krishnamurthy, R., Mathew, S., Anders, M., Hsu, S., Kaul, H. and Borkar, S.: High-performance and low-voltage challenges for sub-45nm microprocessor circuits, 6th International Conference On ASIC, 2005, Vol.1, pp.283-286, IEEE (2006).
• 2) Joseph, R. and Martonosi, M.: Run-time power estimation in high performance microprocessors, Proc. 2001 International Symposium on Low Power Electronics and Design, pp.135-140, ACM (2001).
• 3) Jotwani, R., Sundaram, S., Kosonocky, S., Schaefer, A., Andrade, V., Constant, G., Novak, A. and Naffziger, S.: An x86-64 core implemented in 32nm SOI CMOS, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp.106-107, IEEE (2010).
• 4) Kumar, R. and Hinton, G.: Solid-State Circuits Conference-Digest of Technical Papers, 2009, ISSCC 2009, IEEE International, pp.58-59, IEEE (2009).
• 5) Kanno, Y.: Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor, ISSCC 2006, pp.540-541 (2006).

Terms in the title (6)： マイクロプロセッサ ,  機能ユニット ,  微粒 ,  パワーゲート ,  設計 ,  実装