Art

J-GLOBAL ID：201202218843419715   Reference number：12A0607534

A proper security analysis method for CMOS cryptographic circuits

CMOS暗号回路に適した安全性解析法

Author (3)： TAKAHASHI Yoshio (NTT DATA Corp., Res. and Dev. Headquarters) ,  TAKAHASHI Yoshio (Graduate School of Environment and Information Sciences, Yokohama National Univ.) ,  MATSUMOTO Tsutomu (Graduate School of Environment and Information Sciences, Yokohama National Univ.)
Material： IEICE Electronics Express (Web)  (IEICE Electron Express (Web))
Volume： 9  Issue： 6  Page： 458-463 (J-STAGE)  Publication year： 2012 
JST Material Number： U0039A  ISSN： 1349-2543  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *CMOS structure ,  *electronic circuit ,  *safety analysis ,  *cipher machine ,  *electric power consumption ,  analysis ,  cryptography key ,  secret key cryptosystem ,  transition probability ,  analytical model ,  *safety evaluation ,  ECM ,  *analog circuit ,  circuit simulation ,  Logic ,  NOR circuit ,  gate circuit ,  NAND circuit ,  cyberattack ,  countermeasure ,  *MOS structure
Semi thesaurus term： RSL ,  side channel attack ,  cipher circuit ,  電力差分解析

JST classification (2)： General  (NC03161C) ,  Data protection  (JD01020V)

Reference (8)：

• [1] P. Kocher, J. Jaffe, and B. Jun, “Differential Power Analysis,” CRYPTO '99, LNCS 1666, pp. 388-397, Springer, Aug. 1999.
• [2] T. Ishihara and H. Yasuura, “On Accuracy of Switch Level Power Estimation for CMOS LSI Circuits,” IPSJ, vol. 95, no. 54, pp. 23-30, 1995.
• [3] S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks - Revealing the Secrets of Smart Cards, Springer, 2007, ISBN-13:978-0387308579.
• [4] D. Suzuki, M. Saeki, and T. Ichikawa, “Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level,” IEICE Trans. Fundamentals, vol. E90-A, no. 1, pp. 160-168, 2007.
• [5] K. J. Kulikowski, M. G. Karpovsky, and A. Taubin, “Power Attacks on Secure Hardware Based on Early Propagation of Data,” 12th IEEE International On-Line Testing Symposium, pp. 131-138, July 2006.

Terms in the title (3)： CMOS ,  暗号回路 ,  安全性解析