Art

J-GLOBAL ID：201302209415969253   Reference number：13A0529689

Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP

プロセス代数CSPを使ったシーケンス線図の詳細化と検証

Author (3)： KAIZU Tomohiro (Japan Advanced Inst. of Sci. and Technol.) ,  ISOBE Yoshinao (National Inst. of Advanced Industrial Sci. and Technol.) ,  SUZUKI Masato (Japan Advanced Inst. of Sci. and Technol.)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E96-A  Issue： 2  Page： 495-504 (J-STAGE)  Publication year： 2013 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： software development ,  *drawing(diagram) ,  *object-oriented design ,  UML ,  *program verification ,  CSP ,  computer processing system
Semi thesaurus term： *sequence diagram

JST classification (1)： Computer system development  (JD02010R)

Reference (11)：

• HOARE, C. A. R. Communicationg Sequential Processes. 1985
• ROSCOE, A. W. The Theory and Practice of Concurrency. 1998
• Formal Systems (Europe) Limited. FDR2 User Manual. http://www.fsel.com/fdr2_manual.html
• BUTH, B. Model-checking the architectural design of a fail-safe communication system for railway interlocking systems. FM99. 1999, 1869-1869
• RYAN, P. The modelling and analysis of security protocols : the csp approach. 2001

Terms in the title (5)： プロセス代数 ,  CSP ,  シーケンス ,  線図 ,  検証