Art
J-GLOBAL ID:201402213122831936   Reference number:14A0552716

Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm

基数値推定アルゴリズムを備えた多値巡回ADCの実験実装
Author (4):
Material:
Volume: E97.C  Issue:Page: 308-315 (J-STAGE)  Publication year: 2014 
JST Material Number: U0468A  ISSN: 1745-1353  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: ENGLISH (EN)
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Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
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JST classification (2):
JST classification
Category name(code) classified by JST.
AD/DA conversion circuits  ,  Semiconductor integrated circuit 
Reference (18):
  • [1] M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske, “A 14b 40MS/s redundant SAR ADC with 480MHz clock in 0.13µm CMOS,” Tech. Digest of ISSCC, pp.248-249, San Francisco, Feb. 2007.
  • [2] T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, and T. Mori, “SAR ADC algorithm with redundancy and digital error correction,” IEICE Trans. Fundamentals, vol.E93-A, no.2, pp.415-423, Feb. 2010.
  • [3] S. Lewis and P. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol.SC-22, no.6, pp.954-961, Dec. 1987.
  • [4] S. Lewis, H. Fetterman, G. Gross, Jr., R. Ramachandran, and T. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol.27, pp.351-358, March 1992.
  • [5] T. Cho and P.R. Gray, “A 10-b, 20-Msample/s, 35-mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol.30, pp.166-172, March 1995.
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