Art

J-GLOBAL ID：201402226462422318   Reference number：14A0409114

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters

一グループの非平衡CMOSアービタを用いた2.6~4.2ps分解能を備えたフラッシュTDC

Author (6)： KOMATSU Satoshi (VLSI Design and Education Center (VDEC), The Univ. of Tokyo) ,  J. YAMAGUCHI Takahiro (ADVANTEST Laboratories Ltd.) ,  ABBAS Mohamed (VLSI Design and Education Center (VDEC), The Univ. of Tokyo) ,  MAI KHANH Nguyen Ngoc (VLSI Design and Education Center (VDEC), The Univ. of Tokyo) ,  TANDON James (VLSI Design and Education Center (VDEC), The Univ. of Tokyo) ,  ASADA Kunihiro (VLSI Design and Education Center (VDEC), The Univ. of Tokyo)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E97-A  Issue： 3  Page： 777-780 (J-STAGE)  Publication year： 2014 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 短報  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *semiconductor integrated circuit ,  *electronic circuit ,  time resolution ,  flash memory ,  *signal converter ,  binding and coupling ,  NAND circuit ,  adjustment ,  library(computer) ,  computer program
Semi thesaurus term： *CMOS circuit ,  *arbiter ,  cell library ,  Timing offset ,  macros ,  cross linkage ,  *time to digital converter

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Other electronic circuits  (NC05090X)

Reference (7)：

• [1] J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. Thillo, and J. Craninckx, “A 86MHz-12GHz digital-intensive PLL for software-defined radios, using a 6fJ/step TDC in 40nm digital CMOS,” IEEE J. Solid-State Circuits, vol.45, no.10, pp.2116-2129, Oct. 2010.
• [2] P.M. Levine and G.W. Roberts, “High-resolution flash time-to-digital conversion and calibration for system-on-chip testing,” IEE Proc. Comput. Digit. Tech., vol.152, no.3, pp.415-426, May 2005.
• [3] V. Gutnik and A. Chandrakasan, “On-chip picosecond time measurement,” IEEE Symp. on VLSI Circuits Dig. Tech. Papers, pp.52-53, June 2000.
• [4] N. Minas, D. Kinniment, K. Heron, and G. Russel, “A high-resolution flash TDC taking into account process variability,” Proc. IEEE Int. Sym. Asynchronous Circuits Syst., pp.163-174, Berkeley, CA, March 2007.
• [5] M. Zanuso, S. Levantino, A. Puggelli, C. Samori, and A.L. Lacaita, “TDC with 3-ps resolution and digital linearization algorithm,” Proc. European Solid-State Circuits Conference, pp.262-265, Sept. 2010.

Terms in the title (7)： グループ ,  非平衡 ,  CMOS ,  アービタ ,  分解能 ,  フラッシュ ,  TDC