Art

J-GLOBAL ID：201402297533966220   Reference number：13A1955882

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits

順序回路におけるソフトエラー伝播解析のための効率的故障シミュレーションアルゴリズム

Author (3)： TAKATA Taiga (Cadence Design Systems) ,  YOSHIMURA Masayoshi (Dep. of Advanced Information Technol., Graduate School of Information Sci. and Electrical Engineering, Kyushu Univ.) ,  MATSUNAGA Yusuke (Dep. of Advanced Information Technol., Graduate School of Information Sci. and Electrical Engineering, Kyushu Univ.)
Material： IPSJ Transactions on System LSI Design Methodology (Web)  (情報処理学会論文誌トランザクション System LSI Design Methodology(Web))
Volume： 6  Page： 127-134 (J-STAGE)  Publication year： 2013 
JST Material Number： U0110A  ISSN： 1882-6687  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： Computer Simulation ,  *fault diagnosis ,  *algorithm ,  *efficiency ,  exact solution ,  heuristics ,  acceleration (velocity) ,  sequental circuit ,  soft error ,  propagation (transmission) ,  heuristic algorithm ,  computer application ,  utilization
Semi thesaurus term： exact algorithm ,  *fault simulation ,  *Effective algorithm ,  propagation

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (9)：

• [1] von Neuman, J.: Probablistic Logics and Synthesis of Reliable Organisms from Unreliable Components, Automatic Studies, Shannon, C. and McCarthy, J. (Eds.), pp.43-98, Princeton University Press (1956).
• [2] Cheng, W.-T. and Yu, M.-L.: Differential Fault Simulation — a Fast Method using Minimal Memory, Proc. 26th Design Automation Conference, pp.424-428 (1989).
• [3] Alexandrescu, D. and Costenaro, E.: Towards Optimized Functional Evaluation of SEE-Induced Failures in Complex Designs, Proc. 18th IEEE International On-Line Testing Symposium, pp.182-187 (2012).
• [4] Yoshimura, M., Akamine, Y. and Matsunaga, Y.: A Soft Error Tolerance Estimation Method for Sequential Circuits, Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp.268-276 (2011).
• [5] Miskov-Zivanov, N. and Marculescu, D.: MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits, Proc. 43rd ACM/IEEE Design Automation Conference, pp.767-772 (2006).

Terms in the title (6)： 順序回路 ,  ソフトエラー ,  伝播 ,  解析 ,  故障シミュレーション ,  アルゴリズム