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J-GLOBAL ID:201502202968609760   Reference number:15A0816979

BTB Energy Reduction by Focusing on Useless Accesses

未使用アクセスに注目したBTBエネルギー低減
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Volume: E98.C  Issue:Page: 569-579 (J-STAGE)  Publication year: 2015 
JST Material Number: U0468A  ISSN: 1745-1353  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: ENGLISH (EN)
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Digital computer hardwares in general 
Reference (20):
  • [1] J.K.F. Lee and A.J. Smith, “Branch prediction strategies and branch target buffer design,” Computer, vol.17, no.1, pp.6-22, 1984.
  • [2] J.L. Hennessy and D.A. Patterson, Computer architecture: A quantitative approach, Morgan Kaufmann Publishers, Inc., second edition, 1996.
  • [3] R. Kahn and S. Weiss, “Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers,” Microprocessors and Microsystems, vol.32, no.8, pp.425-436, 2008.
  • [4] H. Sadeghi, H. Sarbazi-Azad, and H.R. Zarandi, “Power-aware branch target prediction using a new BTB architecture,” Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration, pp.53-58, 2009.
  • [5] S.W. Chung and S.B. Park, “A low power branch predictor to selectively access the BTB,” Advances in Computer Systems Architecture Lecture Notes in Computer Science, vol.3189, pp.374-384, Springer, 2004.
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