Art

J-GLOBAL ID：201502235173045707   Reference number：15A0677958

Structure optimization for timing in nano scale FinFET

ナノスケールFinFETにおけるタイミングのための構造最適化

Author (16)： KANAMOTO Toshiki (Renesas System Design) ,  KANAMOTO Toshiki (JEITA EDA Technical Committee) ,  AKAMINE Takeichiro (JEITA EDA Technical Committee) ,  AKAMINE Takeichiro (Socionext) ,  AMMO Hiroaki (JEITA EDA Technical Committee) ,  AMMO Hiroaki (Sony) ,  HASEGAWA Takashi (JEITA EDA Technical Committee) ,  HASEGAWA Takashi (Sony LSI Design) ,  SHIMIZU Kouhei (JEITA EDA Technical Committee) ,  SHIMIZU Kouhei (Panasonic Industrial Devices Systems and Technol.) ,  KUMANO Yoshinori (JEITA EDA Technical Committee) ,  KUMANO Yoshinori (RICOH) ,  KAWANO Masaharu (JEITA EDA Technical Committee) ,  KAWANO Masaharu (RICOH) ,  KUROKAWA Atsushi (JEITA EDA Technical Committee) ,  KUROKAWA Atsushi (Hirosaki Univ.)
Material： IEICE Electronics Express (Web)  (IEICE Electron Express (Web))
Volume： 12  Issue： 9  Page： 20150297-20150297 (J-STAGE)  Publication year： 2015 
JST Material Number： U0039A  ISSN： 1349-2543  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *fin(machine element) ,  *FET ,  logic circuit ,  standard cell ,  regulation ,  constraint condition(restriction) ,  *CMOS structure ,  semiconductor process ,  *circuit analysis ,  *LSI ,  standardization ,  *nanostructure ,  *stray capacity ,  *electric resistance ,  modeling ,  *structural optimization ,  *delay characteristic ,  MOSFET ,  gate(semiconductor) ,  *timing analysis ,  leakage current ,  electric power consumption ,  SPICE program ,  circuit simulation ,  spacing
Semi thesaurus term： FinFET ,  geometric constraint ,  standard cell ,  parasitic resistance ,  HSPICE

JST classification (2)： Transistors  (NC03070N) ,  Semiconductor integrated circuit  (NC03162T)

Reference (10)：

• [1] S. Chaudhuri, P. Mishra and N. K. Jha: International Conference on VLSI Design (2012) 238. DOI:10.1109/VLSID.2012.77
• [2] M. Alioto: IEEE International Symposium on Circuits and Systems (2010) 3204. DOI:10.1109/ISCAS.2010.5537930
• [3] BSIM-CMG (Berkeley Short-channel IGFET Model - Common Multi-Gate) 107.0.0 (2013) http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG.
• [4] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor and C. Hu: IEEE Trans. Electron Dev. 47 (2000) 2320. DOI:10.1109/16.887014
• [5] Synopsys Corp.: Raphael Interconnect Analysis Program Reference Manual, Version D-2010.03 (2010).

Terms in the title (3)： ナノスケール ,  FinFET ,  構造最適化