Rchr
J-GLOBAL ID:201601012444697255
Update date: Apr. 06, 2024
Kobayashi Masaharu
コバヤシ マサハル | Kobayashi Masaharu
Affiliation and department:
Homepage URL (1):
http://nano-lsi.iis.u-tokyo.ac.jp/
Research field (3):
Electrical power engineering
, Electronic devices and equipment
, Electronic devices and equipment
Research keywords (8):
機械学習
, AI
, Ferroelectric device
, Integrated Device
, IoT
, Low power device
, Memory device
, CMOS transistor
Research theme for competitive and other funds (12):
- 2021 - 2024 酸化物半導体と強誘電体HfO2の融合による三次元集積デバイスとその応用技術の創出
- 2021 - 2024 超低電力ニューロモルフィックハードウェア基盤技術のブレークスルー
- 2020 - 2023 ナノスケール強誘電体トランジスタの研究開発と機械学習アクセラレータへの応用
- 2019 - 2022 原子層ヘテロ構造の完全制御成長と超低消費電力・3次元集積デバイスの創出
- 2018 - 2021 Research and development of nanosheet wireless probe enabling multiple and simultaneous probe for neuron activity signal and neurotransmitter
- 2018 - 2021 Exploratory research on ultralow power system based on CMOS compatible ferroelectric devices
- 2018 - 2019 ストレージメモリおよび人工知能ハードウェア応用に向けた強誘電体HfO2トンネル接合メモリのマルチスケールモデリング
- 2015 - 2019 Research and development of steep subthreshold slope transistor by using negative capacitance effect and its applications
- 2018 - 2018 Research and development of ferroelectric HfO2 tunnel junction memory for ultralow power operation based on atomic scale modeling and simulation
- 2017 - 2018 Research and Development of design guideline of ferroelectric HfO2 tunnel junction memory atomic scale based on atomic scale modeling and simulation
- 2016 - 2018 Design and demonstration of ultralow power circuit of steep slope transistor and embedded FeRAM by ferroelectric HfO2
- 2015 - 2017 Ultra-Low Voltage Operating Silicon Nanowire Transistors with Threshold Voltage Self-Adjusting Mechanism
Show all
Papers (342):
-
Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi. A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3-D Integrated Devices. IEEE Transactions on Electron Devices. 2024. 1-7
-
Hirokazu Fujiwara, Yuki Itoya, Masaharu Kobayashi, Cédric Bareille, Shik Shin, Toshiyuki Taniuchi. Nondestructive imaging of breakdown process in ferroelectric capacitors using in situ laser-based photoemission electron microscopy. Applied Physics Letters. 2023. 123. 17
-
Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi. A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2023
-
Masaharu Kobayashi. Monolithic 3D Integration and 3D-Memory Technology Enabled by Oxide-Semiconductor. 2023
-
高橋崇典, 上沼睦典, 小林正治, 浦岡行治. 三次元集積デバイス応用に向けた原子層堆積法で成膜した三元系非晶質酸化物半導体In-Ga-O. 2022年第70回応用物理学会春季学術講演会,上智大学. 2023. 17p-E302-7
more...
MISC (16):
-
後藤 正英, 本田 悠葵, 難波 正和, 井口 義則, 更屋 拓哉, 小林 正治, 日暮 栄治, 年吉 洋, 平本 俊郎. SOIウェハのハイブリッド接合を用いた画素並列3層積層CMOSイメージセンサ-Pixel-Parallel 3-Layer Stacked CMOS Image Sensors Using Hybrid Bonding of SOI Wafers. 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編]. 2022. 39. 5p
-
後藤 正英, 本田 悠葵, 難波 正和, 井口 義則, 更屋 拓哉, 小林 正治, 日暮 栄治, 年吉 洋, 平本 俊郎. SOIウェハのハイブリッド接合を用いた3層積層画素並列CMOSイメージセンサ-3-Layer Stacked Pixel-Parallel CMOS Image Sensors Using Hybrid Bonding of SOI Wafers-情報センシング. 映像情報メディア学会技術報告 = ITE technical report. 2022. 46. 14. 5-8
-
後藤正英, 中谷真規, 本田悠葵, 渡部俊久, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉洋, et al. Multi-Layer Stacking Technology for Pixel-Parallel CMOS Image Sensors by Using Room-Temperature Wafer Bonding. 映像情報メディア学会冬季大会講演予稿集(CD-ROM). 2020. 2020
-
本田悠葵, 後藤正英, 渡部俊久, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉洋, 平本俊郎. 3次元構造撮像素子の高集積化に向けた直接接合による多層積層技術. 映像情報メディア学会年次大会講演予稿集(CD-ROM). 2019. 2019
-
小林 正治, 上山 望, 蔣 京珉, 平本 俊郎. 招待講演 強誘電体HfO2を用いた負性容量トランジスタの動作速度に関する実験検討 (シリコン材料・デバイス). 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2017. 116. 445. 51-54
more...
Patents (11):
-
不揮発性記憶素子
-
Process variability tolerant hard mask for replacement metal gate finFET devices
-
III-V compound semiconductor material passivation with crystalline interlayer
-
Transistor formation using cold welding
-
Method and structure for compound semiconductor contact
more...
Education (3):
- 2006 - 2010 Stanford University Electrical Engineering
- 2004 - 2006 The University of Tokyo Electrical Engineering
- 2000 - 2004 The University of Tokyo Liberal arts/School of Engineering Electronics and Information Engineering
Professional career (1):
Work history (9):
- 2019/10 - 現在 The University of Tokyo
- 2014/05 - 現在 The University of Tokyo Institute of Industrial Science Associate Professor
- 2019/04 - 2019/09 The University of Tokyo VLSI (Very Scale Integration Large) Design and Education Center
- 2010/02 - 2014/04 IBM corporation Watson Research Center Research Staff Member
- 2006/09 - 2010/01 Stanford University Ph.D degree
- 2009/06 - 2009/09 IMEC Visiting Researcher
- 2006/04 - 2006/08 The University of Tokyo Institute of Industrial Science Post master researcher
- 2004/04 - 2006/03 The University of Tokyo Institute of Industrial Science Master
- 2000/04 - 2004/03 The University of Tokyo Bachelor
Show all
Committee career (11):
- 2019/04 - 現在 応用物理学会 JJAP/APEX論文編集委員
- 2018/04 - 現在 電気学会 技術調査専門委員会
- 2018/04 - 現在 IEEE Electron Device Society (EDS) Japan Joint Chapter 幹事
- 2018/04 - 現在 IEEE International Electron Device Meeting (IEDM) サブコミッティー
- 2017/04 - 現在 応用物理学会 プログラム編集委員
- 2015/04 - 現在 電子情報通信学会 ELEX論文編集委員
- 2015/04 - 現在 VLSI technology symposium プログラム委員
- 2015/04 - 現在 International Conference on Solid State Devices and Materials (SSDM) 論文委員
- 2014/04 - 現在 学振165委員会 幹事
- 2015/06 - 2019/06 電子情報通信学会 論文編集委員
- 2017/09 - 2018/09 International Conference on Solid State Devices and Materials (SSDM) 実行委員
Show all
Awards (16):
- 2024/02 - IEEE EDS Japan Joint Chapter IEEE EDS Japan Joint Chapter Student Award A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-Off Operation, High Mobility and Reliability for 3D Integrated Devices
- 2023/12 - IEEE EDS Leo Esaki Award Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model
- 2022/12 - IEEE EDS IEEE EDS Paul Rappaport Award Monolithic Integration of Oxide Semiconductor FET and Ferroelectric Capacitor Enabled y Sn-Doped InGaZnO for 3-D Embedded RAM Application
- 2021/08 - Silicon Nano Workshop Best Student Paper Award Experimental Demonstration of HfO2-based Ferroelectric FET with MoS2 Channel for High-Density and Low-Power Memory Application
- 2020/12 - IEEE EDS IEEE EDS Leo Esaki Award Ferroelectric HfO2 Tunnel Junction Memory with High TER and Multi-level Operation Featuring Metal Replacement Process
- 2020/11 - キオクシア キオクシア奨励研究デバイス部門 優秀研究賞 ストレージメモリおよび人工知能ハードウェア応用に向けた強誘電体HfO2トンネル接合メモリのマルチスケールモデリング
- 2020/04 - Ministry of Education, Culture, Sports, Science and Technology The Young Scientist Award of the year of 2020 Research on innovative transistor and memory technologies based on next generation ferroelectric materials
- 2020/03 - 丸文財団 令和元年度丸文研究奨励賞を受賞 HfO2系強誘電体を用いた次世代集積回路素子の研究
- 2020/02 - IEEE EDS Japan Joint Chapter IEEE EDS Japan Chapter Student Award "Experimental Demonstration of Ferroelectric HfO2 FET with Ultrathin-body IGZO for High-Density and Low-Power Memory Application"
- 2020/02 - IEEE EDS Japan Joint Chapter IEEE EDS Japan Chapter Student Award(2/7) "Transient Negative Capacitance as Cause of Reverse Drain-induced Barrier Lowering and Negative Differential Resistance in Ferroelectric FETs"
- 2019/05 - 電子情報通信学会 ICD Poster award in the Workshop on LSI and System 強誘電体HfO2を用いた低消費電力トランジスタ・メモリ技術の新展開
- 2019/03 - 応用物理学会 第46回(2019年春季)応用物理学会講演奨励賞(3/10) Polarization Switching as the Cause of Steep Subthreshold Slope in Ferroelectric FETs
- 2019/01 - IEEE EDS Japan Joint Chapter IEEE EDS Japan Chapter Student Award 2 Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method with Self-consistent Potential
- 2019/01 - IEEE EDS Japan Joint Chapter IEEE EDS Japan Chapter Student Award Experimental Study on the Role of Polarization Switching in Subthreshold Characteristics of HfO2-based Ferroelectric and Anti-ferroelectric FET
- 2018/07 - IEEE Nanotechnology Council Best paper award Negative Capacitance for Booting Tunnel FET Performance
- 2013/02 - IBM Outstanding contribution award 14nm SOI technology development
Show all
Association Membership(s) (4):
THE JAPANESE SOCIETY FOR ARTIFICIAL INTELLIGENCE
, THE INSTITUTE OF ELECTRICAL ENGINEERS OF JAPAN
, IEEE
, THE JAPAN SOCIETY OF APPLIED PHYSICS
Return to Previous Page