Art
J-GLOBAL ID：201602011931198156   Reference number：72A0270624

An efficient algorithm for generating complete testsets for combinational logic circuits.

組合せ論理回路の完全検査集合を生成する効率のよいアルゴリズム
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Author (2)：
YAU S S

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, 
TANG Y-S

About TANG Y-S


Material：
IEEE Trans Comput  (IRE Transactions on Electronics Computers)

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Volume： 20  Issue： 11  Page： 1245-1251  Publication year： 1971 
JST Material Number： C0233A  ISSN： 0018-9340  CODEN： ICTOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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アルゴリズム

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, 
故障診断

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, 
組合せ回路

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, 
論理回路

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Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
Boole微分

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, 
論理検査

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Terms in the title (5)：
Terms in the title
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組合せ

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, 
論理回路

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, 
検査

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, 
集合

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, 
アルゴリズム

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