Art

J-GLOBAL ID：201602217853224950   Reference number：16A0621888

Design and Evaluation of a Multicore Dataflow DSP with Modified Ring Interconnection Networks

修正したリング相互結合網を有するマルチコアデータフローDSPの設計と評価

Author (3)： ICHIJO Kenji (Hirosaki Univ., Hirosaki, JPN) ,  KUBOTA Masato (Hirosaki Univ., Hirosaki, JPN) ,  NARITA Akiko (Hirosaki Univ., Hirosaki, JPN)
Material： Information (Koganei)
Volume： 19  Issue： 6(B)  Page： 2403-2417  Publication year： Jun. 2016 
JST Material Number： L7416A  ISSN： 1343-4500  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *interconnection network ,  *microprocessor ,  *digital signal processor ,  parallel arithmetic ,  signal processing ,  FPGA ,  matrix (mathematics) ,  *multi-core processor
Semi thesaurus term： digital signal processing ,  *data flow ,  *multi-core ,  massive parallel computing

JST classification (1)： Special-purpose arithmetic and control units  (JC04030Y)

Reference (15)：

• K. Ichijo and K. Nitobe, Design and Evaluation of a Ring Interconnected Multicore Dataflow DSP with a Low Cost Fault Tolerant Mechanism, INFORMATION , Vol. 17, No.1 (2014), 99-110.
• K. Ichijo, K. Niiyama and Y. Yoshioka, Comparative Evaluation of LSC-Based DSP with five kinds of link width, INFORMATION, Vol.13, No.3(B) (2010), 1047-1054.
• K. Niiyama, K. Ichijo and Y. Yoshioka, Execution time measurement of a vector operation on LSC-Based DSP, Proceedings of International Conference on ISPACS (2009), 1-8.
• K. Ichijo and Y. Yoshioka, Efficient Implementation of the Vector Operation on the Loop Structured Computer, Proceedings of the International Conference on PDPTA (2003), 338-344.
• K. Ichijo and Y. Yoshioka, Performance Simulation of the Vector Operation on the Loop Structured Computer, Proceedings of the 3th International Conference on PDCAT (2002), 469-474.

Terms in the title (4)： 相互結合網 ,  DSP ,  設計 ,  評価