Art

J-GLOBAL ID：201602233037032309   Reference number：16A1366675

Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences

頻出ビット列圧縮によるキャッシュメモリのデータ利用効率の向上

Author (3)： KOBAYASHI Ryotaro (Graduate School of Engineering, Toyohashi University of Technology) ,  KANEKO Ikumi (Graduate School of Engineering, Toyohashi University of Technology) ,  SHIMADA Hajime (Nagoya University)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E99.C  Issue： 8  Page： 936-946(J-STAGE)  Publication year： 2016 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *cache memory ,  microprocessor ,  electric power consumption ,  Data Compression ,  binary logic ,  main memory ,  *frequency (statistics) ,  *memory hierarchy ,  arithmetic processor
Semi thesaurus term： *access frequency ,  bit pattern ,  processor ,  *memory hierarchy

Author keywords (3)： cache memory ,  low power ,  frequent bit sequences

JST classification (2)： Memory systems  (JC02040V) ,  Control systems  (JC02030K)

Reference (20)：

• [1] K. Ghose and M.B. Kamble, “Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation,” Proceedings of the 1999 International Symposium on Low Power Electronics and Design, pp.70-75, 1999.
• [2] C.-L Yang and C.-H. Lee, “Hotspot cache: joint temporal and spatial locality exploitation for i-cache energy reduction,” Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp.114-119, 2004.
• [3] N. Suzuki, M. Urahama, and Y. Tokunaga, “ARM946E-S core low-power desing method (device articles),” Oki Technical Review, vol.72, no.3, pp.52-55, 2005.
• [4] K. Oka, H. Sasaki, and K. Inoue, “Line sharing cache: Exploring cache capacity with frequent line value locality,” Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference, pp.669-674, 2013.
• [5] J. Yang, Y. Zhang, and R. Gupta, “Frequent value compression in data caches,” Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pp.258-265, 2000.

Terms in the title (2)： キャッシュメモリ ,  利用効率