Art

J-GLOBAL ID：201702214969927796   Reference number：17A0223306

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

65nmのSOTB CMOS技術におけるきめの細かいボディバイアスを用いる電力の再構成可能なFPGAの低いオーバヘッドの設計

Author (2)： HIOKI Masakazu (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ,  KOIKE Hanpei (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST))
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E99.D  Issue： 12  Page： 3082-3089(J-STAGE)  Publication year： 2016 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： bias ,  Electronics ,  *possibility ,  *FPGA ,  *load ,  atomization (particulate) ,  consumed electric power ,  memory (computer) ,  CMOS technology
Semi thesaurus term： body bias ,  *reconfigurability ,  *overhead ,  field programmable gate array ,  power reduction ,  memory

Author keywords (4)： FPGA ,  programmable V_t ,  body biasing ,  static power

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (19)：

• [1] F. Li, Y. Lin, L. He, and J. Cong, “Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics,” Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp.42-50, 2004.
• [2] A. Rahman and V. Polavarapuv, “Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays,” Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp.23-30, 2004.
• [3] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, and T. Tuan, “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement,” Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp.51-58, 2004.
• [4] J.H. Anderson and F.N. Najim, “Low-power programmable routing circuitry for FPGAs,” Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, pp.602-609, 2004.
• [5] Y. Lin, F. Li, and L. He, “Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction,” Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pp.645-650, 2005.

Terms in the title (6)： CMOS技術 ,  ボディバイアス ,  再構成 ,  FPGA ,  オーバヘッド ,  設計