Art

J-GLOBAL ID：201702242011627481   Reference number：17A1619390

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

キャプチャセーフテストベクトル操作に基づく低キャプチャパワーテスト生成法

Author (4)： HOSOKAWA Toshinori (College of Industrial Technology, Nihon University) ,  HIRAI Atsushi (Graduate School of Industrial Technology, Nihon University) ,  YAMAUCHI Yukari (College of Industrial Technology, Nihon University) ,  ARAI Masayuki (College of Industrial Technology, Nihon University)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E100.D  Issue： 9  Page： 2118-2125(J-STAGE)  Publication year： 2017 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *test ,  *vector(mathematics) ,  bistable circuit ,  *voltage drop ,  electric power consumption ,  yield
Semi thesaurus term： *キャプチャセーフテストベクトル ,  test ,  *test generation ,  flip-flop circuit

Author keywords (5)： low power ,  test generation ,  capture safe test vectors ,  test vector synthesis ,  unsafe faults

JST classification (1)： Other computer utilization technology  (JE14000C)

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