Art

J-GLOBAL ID：201702246402529174   Reference number：17A1024503

Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles

複素および実極のための高速RLC相互接続遅延の解析モデル【Powered by NICT】

Author (2)： Ullah Muhammad S. (Department of Computer Science Electrical Engineering, University of Missouri-Kansas City, Kansas City, MO, USA) ,  Chowdhury Masud H. (Department of Computer Science Electrical Engineering, University of Missouri-Kansas City, Kansas City, MO, USA)
Material： IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (IEEE Trans Very Large Scale Integr Syst)
Volume： 25  Issue： 6  Page： 1831-1841  Publication year： 2017 
JST Material Number： W0516A  ISSN： 1063-8210  CODEN： ITCOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)

Abstract/Point： Continuous shrinking of the si...

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Thesaurus term： interconnection network ,  optimization ,  integrated circuit ,  *interconnection ,  real number ,  transistor ,  approximation method ,  *high speed ,  simulation ,  transfer function ,  *analytical model ,  stray capacity
Semi thesaurus term： 寄生効果 ,  超高速 ,  CMOS技術 , 【Automatic Indexing@JST】

JST classification (2)： General  (NC03161C) ,  Semiconductor integrated circuit  (NC03162T)

Terms in the title (4)： 極 ,  相互接続 ,  遅延 ,  解析モデル