Art

J-GLOBAL ID：201702247094251020   Reference number：17A0980550

Coverage-Driven Design Verification Using a Diverse SAT Solver

多様なSATソルバーを用いたカバレッジ駆動型設計検証

Author (2)： KAKIUCHI Yosuke (Department of Computer Science, Faculty of Applied Information Science, Hiroshima Institute of Technology) ,  HAMAGUCHI Kiyoharu (Department of Mathematics and Computer Science, Shimane University)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E100.A  Issue： 7  Page： 1481-1487(J-STAGE)  Publication year： 2017 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *integrated circuit ,  *logic circuit ,  *logical design ,  *verification ,  satisfiability problem ,  application program ,  *automatic test ,  inspection ,  solver
Semi thesaurus term： RTL ,  test bench ,  *design verification

Author keywords (4)： RTL verification ,  coverage-driven verification ,  sat solver ,  auomated testbench

JST classification (2)： General  (NC03161C) ,  Logic circuits  (NC05070B)

Reference (16)：

• [1] A. Nadel, “Generating diverse solutions in SAT,” Theory and Applications of Satisfiability Testing-SAT, pp.287-301, 2011. 10.1007/978-3-642-21581-0_23
• [2] S. Yang, R. Wille, and R. Drechsler, “Determining cases of scenarios to improve coverage in simulation-based verification,” Symp. on Integrated Circuits and System Design, 2014. 10.1145/2660540.2660979
• [3] S. Yang, R. Wille, D. Große, and R. Drechsler,“Coverage-driven stimuli generation,” EUROMICRO Symp. on Digital System Design, pp.525-528, 2012. 10.1109/dsd.2012.37
• [4] S. Chakraborty, K.S. Meel, and M.Y. Vardi, “A scalable and nearly uniform generator of SAT witnesses,” Computer-Aided Verification, pp.608-623, 2013. 10.1007/978-3-642-39799-8_40
• [5] I. Wagner, V. Bertacco, and T. Austin, “Microprocessor verification via feedback-adjusted Markov models,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.26, no.6, pp.1126-1138, 2007. 10.1109/tcad.2006.884494

Terms in the title (4)： SAT ,  ソルバー ,  カバレッジ ,  設計検証