Art

J-GLOBAL ID：201802225958166455   Reference number：18A0656544

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device

フレックスパワーFPGAデバイスの評価用プラットフォームの開発と性能実験

Author (4)： KATASHITA Toshihiro (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology) ,  HIOKI Masakazu (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology) ,  HORI Yohei (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology) ,  KOIKE Hanpei (Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E101.D  Issue： 2  Page： 303-313(J-STAGE)  Publication year： 2018 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *flexibility ,  *semiconductor device ,  *FPGA ,  *computer system (hardware) ,  *evaluation ,  fast computation ,  consumed electric power ,  power efficiency ,  bias ,  frequency (Hz) ,  voltage ,  adder ,  multiplier ,  *platform ,  operating frequency ,  operating voltage ,  threshold voltage
Semi thesaurus term： *power device ,  body bias ,  low electric power

Author keywords (4)： FPGA ,  programmable body biasing ,  evaluation platform ,  static power consumption

JST classification (2)： Digital computer systems in general  (JC02010O) ,  General  (NC03161C)

Reference (12)：

• [1] T. Kawanami, M. Hioki, H. Nagase, T. Tsutsumi, T. Nakagawa, T. Sekigawa, and H. Koike, “Preliminary evaluation of flex power FPGA: A power reconfigurable architecture with fine granularity,” IEICE Trans. Inf. & Syst., vol.E87-D, no.8, pp.2004-2010, Aug. 2004.
• [2] M. Hioki, T. Katashita, and H. Koike, “Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp.105-107, 2016. 10.1109/s3s.2016.7804400
• [3] M.J.S. Smith, Application-Specific Integrated Circuits, Addison Wesley, 1999.
• [4] R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control,” IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.631-634, 2004. 10.1109/iedm.2004.1419245
• [5] M. Hioki and H. Koike, “Low overhead design of power reconfigurable FPGA with fine-grained body biasing on 65-nm SOTB CMOS technology,” IEICE Trans. Inf. & Syst., vol.E99-D, no.12, pp.3082-3089, Dec. 2016. 10.1587/transinf.2016edp7129

Terms in the title (7)： フレックス ,  パワー ,  FPGA ,  評価 ,  プラットフォーム ,  開発 ,  実験