Art

J-GLOBAL ID：201802254561634856   Reference number：18A0994669

A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique

面積効率の良い確率的オフセット電圧検出技術を用いた動的ラッチコンパレータ

Author (2)： OKAZAWA Takayuki (Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology) ,  AKITA Ippei (Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E101.C  Issue： 5  Page： 396-403(J-STAGE)  Publication year： 2018 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *methodology ,  *voltage ,  *detection method ,  *latching circuit ,  *comparator ,  calibration ,  uncertainty ,  semiconductor process
Semi thesaurus term： CMOS process ,  *offset voltage ,  確率的 ,  *probabilistic method ,  calibration ,  *detection technique

Author keywords (3)： dynamic latched comparator ,  self-calibrating ,  stochastic offset voltage detection

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  AD/DA conversion circuits  (NC05080M)

Reference (18)：

• [1] K. Uyttenhove and M.S.J. Steyaert, “Speed-power-accuracy tradeoff in high-speed CMOS ADCs,” IEEE Trans. Circuits Syst. II, vol.49, no.4, pp.280-287, April 2002. 10.1109/tcsii.2002.801191
• [2] P.R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, vol.40, no.6, pp.1212-1224, June 2005. 10.1109/jssc.2005.848021
• [3] J. He, S. Zhan, D. Chen, and R.L. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits Syst. I, vol.56, no.5, pp.911-919, May 2009. 10.1109/tcsi.2009.2015207
• [4] G. Van der Plas, J. Vandenbussche, W. Verhaegen, G. Gielen, and W. Sansen, “Statistical behavioral modeling for A/D-converters,” Proc. IEEE Int. Conf. Electronics, Circuits Syst., pp.1713-1716, Sept. 1999. 10.1109/icecs.1999.814506
• [5] A. Matsuzawa, “High speed and low power ADC design with dynamic analog circuits,” Proc. IEEE Int. Conf. ASIC, pp.218-221, Oct. 2009. 10.1109/asicon.2009.5351489

Terms in the title (5)： 面積効率 ,  確率 ,  オフセット電圧 ,  検出技術 ,  コンパレータ