Art

J-GLOBAL ID：201802261782769731   Reference number：18A1236919

Impact of mutual inductance on timing in nano-scale SoC

ナノスケールSoCにおけるタイミングに及ぼす相互インダクタンスの影響

Author (8)： Sakata Kazuyuki (Renesas Electronics Corp.) ,  Sakata Kazuyuki (JEITA Semiconductor & System Design Technical Committee) ,  Hasegawa Takashi (JEITA Semiconductor & System Design Technical Committee) ,  Hasegawa Takashi (Sony LSI Design) ,  Ichikawa Kouji (JEITA Semiconductor & System Design Technical Committee) ,  Ichikawa Kouji (DENSO CORPORATION) ,  Kanamoto Toshiki (JEITA Semiconductor & System Design Technical Committee) ,  Kanamoto Toshiki (Hirosaki University)
Material： IEICE Electronics Express (Web)  (IEICE Electron Express (Web))
Volume： 15  Issue： 11  Page： 20180376(J-STAGE)  Publication year： 2018 
JST Material Number： U0039A  ISSN： 1349-2543  Document type： Article
Article type： 短報  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *scale ,  *VLSI ,  *delay ,  *mutual inductance ,  rule ,  parameter ,  inductance ,  electrostatic capacity ,  resistance
Semi thesaurus term： *SOC ,  capacitance ,  *nanoscale ,  design rule ,  *wire delay ,  physical parameter

Author keywords (7)： on chip inductance ,  mutual ,  screening ,  delay ,  timing analysis ,  nano-scale ,  system on a chip

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Computer simulation  (JE11000H)

Reference (17)：

• [1] K. Banerjee and A. Mehrotra: “Analysis of on-chip inductance effects for distributed RLC interconnects,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21 (2002) 904 (DOI: 10.1109/TCAD.2002.800459).
• [2] T. Sato, et al.: “Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF,” The ASP-DAC Asia and South Pacific Design Automation Conference (2003) 149 (DOI: 10.1109/ASPDAC.2003.1195008).
• [3] A. Roy, et al.: “Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18 (2010) 338 (DOI: 10.1109/TVLSI.2008.2011911).
• [4] T. Murgan, et al.: “Timing and power consumption in high-speed very deep sub-micron on-chip interconnects,” J. Integr. Circuits Syst. 1 (2006) 25.
• [5] M. S. Ullah and M. H. Chowdhury: “Analytical models of high-speed RLC interconnect delay for complex and real poles,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 1831 (DOI: 10.1109/TVLSI.2017.2654921).

Terms in the title (3)： ナノスケール ,  SOC ,  相互インダクタンス