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J-GLOBAL ID：201802281065164621   Reference number：18A1044349

Scalable deep neural network accelerator cores with cubic integration using through chip interface

スルーチップインタフェイスを用いた3次集積によるスケーラブルなディープニューラルネットワーク加速器コア【JST・京大機械翻訳】

Author (8)： Sakamoto Ryuichi (Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan) ,  Takata Ryo (Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan) ,  Ishii Jun (Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan) ,  Kondo Masaaki (Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan) ,  Nakamura Hiroshi (Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan) ,  Ohkubo Tetsui (Department of Information and Computer Science, Keio University, Yokohama, Japan) ,  Kojima Takuya (Department of Information and Computer Science, Keio University, Yokohama, Japan) ,  Amano Hideharu (Department of Information and Computer Science, Keio University, Yokohama, Japan)
Material： IEEE Conference Proceedings  (IEEE Conf Proc)
Volume： 2017  Issue： ISOCC  Page： 155-156  Publication year： 2017 
JST Material Number： W2441A  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)

Abstract/Point： Due to the recent advances in ...

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Thesaurus term： algorithm ,  *neural network (biomodel) ,  power efficiency ,  flexibility ,  portable telephone ,  application program ,  computer architecture ,  *accelerator ,  *interface ,  *network ,  embedded system ,  *deep neural network
Semi thesaurus term： LSI設計 , 【Automatic Indexing@JST】

JST classification (2)： Special-purpose arithmetic and control units  (JC04030Y) ,  Computer networks  (JC03000K)

Terms in the title (4)： 集積 ,  ディープニューラルネットワーク ,  加速器 ,  コア