Art

J-GLOBAL ID：201902017186582127   Reference number：19S2751754

A 10-ns 54 × 54-b Parallel Structured Full Array Multiplier with 0.5-μm CMOS Technology

Author (9)： Mori, Junji (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Nagamatsu, Masato (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Hirano, Masashi (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Tanaka, Shigeru (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Noda, Makoto (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Toyoshima, Yoshiaki (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Hashimoto, Kazuhiro (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Hayashida, Hiroyuki (Semiconductor Device Engineering Laboratory, Toshiba Corporation) ,  Maeguchi, Kenji (Semiconductor Device Engineering Laboratory, Toshiba Corporation)
Material： IEEE Journal of Solid-State Circuits
Volume： 26  Issue： 4  Page： 600-606  Publication year： 1991 
JST Material Number： SCOPUS  ISSN： 0018-9200 
Language： English (EN)

Terms in the title (1)： CMOS