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J-GLOBAL ID：201902109237488904   Reference number：19S2877984

1-V high-speed MTCMOS circuit scheme for power-down applications

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Author (4)：
Shigematsu, Satoshi

About Shigematsu, Satoshi

(NTT LSI Lab)

About NTT LSI Lab

, 
Mutoh, Shin ichiro

About Mutoh, Shin ichiro

(NTT LSI Lab)

About NTT LSI Lab

, 
Matsuya, Yasuyuki

About Matsuya, Yasuyuki

(NTT LSI Lab)

About NTT LSI Lab

, 
Yamada, Junzo

About Yamada, Junzo

(NTT LSI Lab)

About NTT LSI Lab


Material：
IEEE Symposium on VLSI Circuits, Digest of Technical Papers

About IEEE Symposium on VLSI Circuits, Digest of Technical Papers


Page： 125-126  Publication year： 1995 
JST Material Number： SCOPUS  CODEN： 85PXA 
Terms in the title (2)：
Terms in the title
Keywords automatically extracted from the title.
MTCMOS

About MTCMOS

, 
Scheme

About Scheme


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