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J-GLOBAL ID：201902214471273545   Reference number：19S0453239

III-V and Ge/strained SOI tunneling FET technologies for low power LSIs

Author (11)： Takagi, S. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Takagi, S. (JST, CREST) ,  Kim, M. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Kim, M. (JST, CREST) ,  Noguchi, M. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Ji, S. M. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Ji, S. M. (JST, CREST) ,  Nishi, K. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Nishi, K. (JST, CREST) ,  Takenaka, M. (Department of Electrical Engineering and Information Systems, University of Tokyo) ,  Takenaka, M. (JST, CREST)
Material： Digest of Technical Papers - Symposium on VLSI Technology
Volume： 2015-August  Page： T22-T23  Publication year： 2015 
JST Material Number： SCOPUS  ISSN： 0743-1562  ISBN： 9784863485013  CODEN： DTPTE 
Country of issue： United States (USA)  Language： English (EN)

Terms in the title (3)： Ge ,  SOI ,  FET