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J-GLOBAL ID：201902220552925547   Reference number：19S1728199

Layout optimization to maximize tolerance in SEILA: Soft error immune latch

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Author (3)：
Uemura, Taiki

About Uemura, Taiki

(Fujitsu Semiconductor Ltd.)

About Fujitsu Semiconductor Ltd.

, 
Sakoda, Tsunehisa

About Sakoda, Tsunehisa

(Fujitsu Semiconductor Ltd.)

About Fujitsu Semiconductor Ltd.

, 
Matsuyama, Hideya

About Matsuyama, Hideya

(Fujitsu Semiconductor Ltd.)

About Fujitsu Semiconductor Ltd.


Material：
2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

About 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011


Publication year： 2011 
JST Material Number： SCOPUS  ISBN： 9781424490202 
Country of issue： United States (USA)  Language： English (EN)

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