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J-GLOBAL ID：201902221264846884   Reference number：19S1191757

Performance evaluation of superscalar processor with multi-bank register file and an implementation result

Author (7)： Tanigawa, Kazuya (Department of Computer Engineering, Hiroshima City University) ,  Hironaka, Tetsuo (Department of Computer Engineering, Hiroshima City University) ,  Maeda, Moto (Department of Computer Engineering, Hiroshima City University) ,  Sueyoshi, Tetsuya (Research Center for Nanodevices and Systems, Hiroshima University) ,  Aoyama, Kenichi (Research Center for Nanodevices and Systems, Hiroshima University) ,  Koide, Tetsushi (Research Center for Nanodevices and Systems, Hiroshima University) ,  Mattausch, Hans Juergen (Research Center for Nanodevices and Systems, Hiroshima University)
Material： WSEAS Transactions on Computers
Volume： 5  Issue： 9  Page： 1993-2000  Publication year： 2006 
JST Material Number： SCOPUS  ISSN： 1109-2750 
Country of issue： Greece (GRC)  Language： English (EN)