Art

J-GLOBAL ID：201902253387560069   Reference number：19A2085359

Process Representation of Sequence Diagrams with Hierarchical Structure

階層的な制御構造をもつシーケンス図間の整合性検証手法の開発

Author (5)： MATSUMOTO AKIRA (岡山県大) ,  YOKOGAWA TOMOYUKI (岡山県大) ,  AMASAKI SOSUKE (岡山県大) ,  AMAN HIROHISA (愛媛大 総合情報メディアセ) ,  ARIMOTO KAZUTAMI (岡山県大)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 119  Issue： 113(KBSE2019 11-22)(Web)  Page： 47-52 (WEB ONLY)  Publication year： Jul. 05, 2019 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： UML ,  finite state machine ,  drawing(diagram) ,  verification ,  *hierarchical structure ,  *program structure ,  transformation and conversion ,  consistency(computer) ,  *model checking
Semi thesaurus term： sequence diagram ,  state machine ,  program control structures ,  model verification ,  automatic conversion ,  consistency

JST classification (1)： Computer system development  (JD02010R)

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Terms in the title (7)： 階層 ,  制御構造 ,  シーケンス図 ,  整合性 ,  検証 ,  手法 ,  開発