Art

J-GLOBAL ID：201902272922846305   Reference number：19A2423659

Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics

Vedic数学を用いた高次浮動小数点乗算器の低電力で面積効率の良い設計【JST・京大機械翻訳】

Author (4)： Loganathan Haripriya (Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India) ,  Rohit Patnaikuni (Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India) ,  Suneel Polamarasetty Sai (Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India) ,  Balasubramanian Karthi (Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India)
Material： Lecture Notes in Electrical Engineering
Volume： 569  Page： 475-486  Publication year： 2020 
JST Material Number： W5070A  ISSN： 1876-1100  Document type： Proceedings
Article type： 原著論文  Country of issue： Germany, Federal Republic of (DEU)  Language： ENGLISH (EN)

Abstract/Point： Floating-point arithmetic unit...

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Thesaurus term： algorithm ,  *multiplier ,  digital method ,  application program ,  operation(mathematics) ,  *multiplication(algebra) ,  trunk(communication network) ,  India
Semi thesaurus term： Verilog ,  古代 ,  信号処理アルゴリズム ,  *面積効率 ,  *低電力化 ,  *浮動小数点 , 【Automatic Indexing@JST】

Author keywords (5)： Floating-point unit ,  IEEE 754 standard ,  Vedic multiplier ,  Urdhva Tiryagbhyam sutra ,  Nikhilam sutra

JST classification (1)： Arithmetic systems  (JC02020Z)

Terms in the title (6)： 数学 ,  浮動小数点 ,  乗算器 ,  低電力 ,  面積効率 ,  設計