Kobayashi Katsushi

コバヤシカツシ | Kobayashi Katsushi

Affiliation and department：
Job title： Unit Lead
Other affiliations (1)：

Ministry of Health, Labour and Welfare Executive Advisor (Information Technology)

Research field (1)： Information networks

Research keywords (2)： Internet Transport , Internet

Research theme for competitive and other funds (7)：

2018 - 2021 Exploring an Internet architecture to support different latenct requirements
2014 - 2018 A bandwidth scale out capable network architecture
2008 - 2014 革新的省エネルギーネットワーク・ルータ技術の研究開発 a)IT社会を遠望した、情報の流れと情報量の調査研究
2011 - 2013 新世代ネットワークを支えるネットワーク仮想化基盤技術の研究開発-大規模コンテンツ配信基盤を実現するアクセス網のクラウド化
2008 - 2011 新世代ネットワークサービス基盤構築技術に関する研究開発 ~ネットワーク「見える化」の実現にむけて~

Show all

Papers (35)：

Katsushi Kobayashi. A DRAM-friendly priority queue Internet packet scheduler implementation and its effects on TCP. IFIP Networking 2020 Conference and Workshops, Networking 2020. 2020. 713-718
Katsushi Kobayashi. LAWIN: A Latency-AWare InterNet architecture for latency support on best-effort networks. IEEE International Conference on High Performance Switching and Routing, HPSR. 2015. 2016-June. 180-187
K. Ishii, F. Okazaki, K. Sato, S. Namiki, D. Mochinaga, K. Kobayashi, H. Takeshita, K. Mizutani, T. Kudoh, J. Kurumida. Unified Approach of Top-down and Bottom-up Methods for Estimating Network Energy Consumption. 39th European Conference and Exhibition on Optical Communication (ECOC 2013). 2013. 2013. 622 CP. 1113-1115
Katsushi Kobayashi. LAWIN: a Latency AWare InterNet architecture: an alternative reducing a latency. ISOC Workshop on Reducing Internet Latency, London, UK. 2013
Design of Authentication System for High Performance Distributed Computing Environment. 2012. 5. 5. 90-102

ｍore...

MISC (38)：

小林克志. A design and implementation of an HBM-based packet scheduler on FPGA. 電子情報通信学会技術研究報告. 2020. 119. 434(SITE2019 88-100). 87-92
小林克志. An evaluation report for EDF-based packet scheduler implementations with a cloud FPGA service. 電子情報通信学会技術研究報告. 2018. 118. 360(IA2018 40-53)(Web)
A scalable packet scheduler to satisfy latency requirements. 2017. 117. 354. 7-12
小林克志. Design and Implementation of FPGA based packet scheduler to satisfy latency requirements of applications. 電子情報通信学会技術研究報告. 2016. 116. 362(IA2016 63-78). 29-34
KOBAYASHI Katsushi. Rethinking network architecture with parallelization. 2015. 114. 518(PN2014 77-99). 81-86

ｍore...

Books (1)：

Lectures and oral presentations (25)：

A design and implementation of an HBM-based packet scheduler on FPGA
(2020)
A scalable packet scheduler to satisfy latency requirements
(2017)
Design and Implementation of FPGA based packet scheduler to satisfy latency requirements of applications
(2016)
Rethinking network architecture with parallelization
(2015)
Design and evaluation of Earliest Deadline First with Reneging packet scheduler : Toward Latency AWare InterNet
(IEICE technical report. Internet Architecture 2014)

ｍore...

Works (5)：

Education (3)：

1990 - 1993 The University of Electro-Communications Graduate School of Electro-Communications Department in Applied Physics and Chemistry
1987 - 1989 The University of Electro-Communications Graduate School of Electro-Communications
1983 - 1987 The University of Electro-Communications Faculty of Electro-Communications

Work history (10)：

2024/04 - 現在 RIKEN Infrastructure Research and Development Division, Advanced Networking Technology Unit Unit Lead
2024/04 - 現在 RIKEN Infrastructure Research and Development Division Unit Leader
2021/09 - 現在 Ministry of Health, Labour and Welfare Executive Advisor for CIO
2022/04 - 2024/03 National Institute of Informatics Project Researcher
2014/04 - 2022/04 The University of Tokyo The Graduate School of Information Science and Technology Project Associate Professor

Show all

Association Membership(s) (3)：

IPSJ , ACM , IEEE

※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

Return to Previous Page