Rchr
J-GLOBAL ID：202001006129221610
Update date: Nov. 03, 2023
Okajima Yoshinori
Okajima Yoshinori
Affiliation and department：
Job title：
代表
Homepage URL (1)：
https://info-integnology.com/index.html
Research field (1)：
High-performance computing
Research keywords (1)：
Info-Integnology Reasearch
Papers (11)：
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Yoshinori Okajima. A conceptual consideration on an interactive computing architecture for the AGI system. 2021
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Yoshinori Okajima. A study on spiking neural network hardware technology. 2020
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Yoshinori Okajima, Adrian Cosoroaba, Hideo Kobayashi. An 0.18 μm embedded FCRAM ASIC with DRAM density and SRAM performance. February 2000ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International. 2000
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July, VLSI Circuits, Digest of Technical Papers, Symposium. All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs. 1997
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Yoshinori Okajima. Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Inteface. 1996
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MISC (4)：
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WAKAYAMA Shigetoshi, GOTOH Kohtaroh, SAITO Miyoshi, OGAWA Junji, TAMURA Hirotaka, OKAJIMA Yoshinori, TAGUCHI Masao. All-Digital Multi-Phase DLL with ±60ps Skew Resolution for High-Speed DRAMs. Technical report of IEICE. SDM. 1997. 97. 195. 115-121
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OKAJIMA YOSHINORI. Interface Technology of SyncLink DRAM. Technical report of IEICE. ICD. 1997. 97. 57. 1-9
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Yoshinori Okajima. A 256-Mb SDRAM using a register-controlled digital DLL. IEEE Journal of Solid-State Circuits. 1997. 97. 56. 17-22
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Yamauchi Tsunenori, Okajima Yoshinori, Kurosaki Kazuhide. Performance Optimization of BiCMOS Circuits under Reduced Supply Voltage. IEEJ Transactions on Electronics, Information and Systems. 1996. 116. 12. 1356-1363
Patents (4)：
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wo2020075658
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JP3982089B2
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PCT/JP2020/015100
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US6097323A
Lectures and oral presentations (2)：
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Study about "A Brief History of Simulation Neuroscience"
(2020)
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NeuroMorphics
(2020)
Works (1)：
Association Membership(s) (2)：
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