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J-GLOBAL ID：202002211421078549   Reference number：20A0873059

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

正確なFPGA時間-ディジタル変換器のための過クロックと二重データレートを持つ高精度PLL遅延行列【JST・京大機械翻訳】

Author (7)： Chen Poki (Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan) ,  Lan Jian-Ting (Himax Technologies Inc., Tainan, Taiwan) ,  Wang Ruei-Ting (Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan) ,  My Qui Nguyen (Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan) ,  Marquez John Carl Joel S. (Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan) ,  Kajihara Seiji (Kyushu Institute of Technology, Fukuoka, Japan) ,  Miyake Yousuke (Kyushu Institute of Technology, Fukuoka, Japan)
Material： IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (IEEE Trans Very Large Scale Integr Syst)
Volume： 28  Issue： 4  Page： 904-913  Publication year： 2020 
JST Material Number： W0516A  ISSN： 1063-8210  CODEN： ITCOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)

Abstract/Point： An extremely high-resolution, ...

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Thesaurus term： high-resolution ,  *clock ,  lapping ,  computer architecture ,  converter ,  resolving power ,  probability distribution ,  phase(topology) ,  digital method ,  phase locked loop ,  *FPGA
Semi thesaurus term： 高精度 ,  *データレート ,  *時間ディジタル変換器 , 【Automatic Indexing@JST】

JST classification (2)： Electronics for elementary and nuclear physics experiments  (BE01020Q) ,  Other electronic circuits  (NC05090X)

Terms in the title (7)： FPGA ,  時間-ディジタル変換器 ,  クロック ,  データレート ,  PLL ,  遅延 ,  行列