Art

J-GLOBAL ID：202002227789504831   Reference number：20A0517788

Design of an SFQ convolutional computation processor for convolutional neural networks

畳込みニューラルネットワーク用SFQ畳込み計算プロセッサの設計

Author (6)： KE Fei (Yokohama National Univ., Yokohama, JPN) ,  REN Ao (Northeastern Univ., MA, USA) ,  WANG Yanzhi (Northeastern Univ., MA, USA) ,  CHEN Olivia (Yokohama National Univ., Yokohama, JPN) ,  YAMANASHI Yuki (Yokohama National Univ., Yokohama, JPN) ,  YOSHIKAWA Nobuyuki (Yokohama National Univ., Yokohama, JPN)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 119  Issue： 369(SCE2019 30-75)  Page： 11-13  Publication year： Jan. 09, 2020 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *flux quantum ,  *arithmetic processor ,  *neural network(biomodel) ,  fast Fourier transformation ,  computer architecture ,  complementary metal oxide semiconductor
Semi thesaurus term： fast Fourier transformation ,  *SFQ(superconduction) ,  architecture ,  *processor ,  *convolutional neuralnetwork ,  deep neural network ,  artificial neural network

JST classification (2)： Josephson junction and elements  (BM04043E) ,  Special-purpose arithmetic and control units  (JC04030Y)

Reference (3)：

• Ding et al, CirCNN accelerating and compressing deep neural networks using block-circulant weight matrices. Proc. 50th Annu. Int. Symp. on Microarchitecture (MICRO), 2017, pp. 395-408.
• Ono, T., Suzuki, H., Yamanashi, Y. & Yoshikawa, N. Design and Implementation of an SFQ-Based Single-Chip FFT Processor. IEEE Trans. Appl. Supercond. 27, 1-5 (2017).
• Mukhanov, O. A. & Kirichenko, A. F. Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders. IEEE Trans. Appl. Supercond. 5, 2461-2464 (1995).

Terms in the title (6)： 畳込みニューラルネットワーク ,  SFQ ,  畳込み ,  計算 ,  プロセッサ ,  設計