Art
J-GLOBAL ID：202002248033528455
Reference number：20A0842793
Vernier Ring Oscillator type first order delta-sigma TDC with counter and delay line
カウンタと遅延器を用いたバーニアリングオシレータ型1次ΔΣTDC
Author (2)：
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Material：
Issue：
ECT-20-027-033.035-040 電子回路研究会
Page：
39-42
Publication year：
Mar. 09, 2020
JST Material Number：
Z0924B
Document type：
Proceedings
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
JAPANESE (JA)
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Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
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JST classification (2)：
JST classification
Category name(code) classified by JST.
Radio communication in general
, AD/DA conversion circuits
Reference (5)：
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R.B. Staszewski, Po. T. Balsara,(著), 山田庸一郎(訳), 小林治夫(監修): 「完全ディジタルPLL回路の設計-ディープ・サブミクロンCMOSプロセスで実現するAll-Digital Frequency Synthesizer」 (2010)
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Y. Osawa, D. Hirabayashi, N.Harigai, H. kobayashi, K. Niitsu, O. Kobayashi, ′′Phase Noise Measurement Techniques Using Delta-Sigma TDC ′′ IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, PortoAlegre, Brazil(Sept. 2014).
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M. Z. Straayer, M. H. Perrott, : A Multi Path Gated Ring Oscillator TDC With First-Order Noise Shaping, IEEE Journal of solid-state circuits, Vol.44, No4, pp1089-1098, (2009)
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C. Chang, Y. Tsai, K. Chein, L. Lu, : A 0.3-V 7.6-fJ/conv-step Delta-Sigma Time-to-Digital Converter with a Gated-Free Ring Oscillator, IEEE International New Circuits and Systems Conference, pp221-224, (2017)
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Z. Cheng, M. J. Deen, H. Peng, : A Low-power gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications, IEEE Transactions on Biomedical Circuits and Systems, Vol.10, No.2, pp445-454, (2016)
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