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J-GLOBAL ID:202002289471649863   Reference number:20A1230935

An Accuracy-Configurable Adder for Low-Power Applications

低電力アプリケーション向けの精度設定可能な加算器
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Volume: E103.C  Issue:Page: 68-76(J-STAGE)  Publication year: 2020 
JST Material Number: U0468A  ISSN: 1745-1353  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: ENGLISH (EN)
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Logic circuits  ,  Graphic and image processing in general 
Reference (18):
  • [1] S. Cotofana, C. Lageweg, and S. Vassiliadis, “Addition related arithmetic operations via controlled transport of charge,” IEEE Trans. Comput., vol.54, no.3, pp.243-256, March 2005. 10.1109/tc.2005.40
  • [2] V. Beiu, S. Aunet, J. Nyathi, R.R. Rydberg, and W. Ibrahim, “Serial Addition: Locally Connected Architectures,” IEEE Trans. Circuits Syst.-I: Regular papers, vol.54, no.11, pp.2564-2579, Nov. 2007. 10.1109/tcsi.2007.907885
  • [3] S. Venkataramani, V.K. Chippa, S.T. Chakradhar, K. Roy, and A. Raghunathan, “Quality programmable vector processors for approximate computing,” 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.1-12, Dec. 2013. 10.1145/2540708.2540710
  • [4] A.B. Kahng and S. Kang, “Accuracy-configurable adder for approximate arithmetic designs,” IEEE/ACM Design Automation Conference (DAC), pp.820-825, June 2012. 10.1145/2228360.2228509
  • [5] R. Ye, T. Wang, F. Yuan, R. Kumar, and Q. Xu, “On reconfiguration-oriented approximate adder design and its application,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.48-54, Nov. 2013. 10.1109/iccad.2013.6691096
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