Art

J-GLOBAL ID：202102264377291077   Reference number：21A0332098

A Degradation Prediction of Circuit Delay Using A Gradient Descent Method

勾配降下法を用いた回路遅延の劣化予測について

Author (5)： MORI SEIICHIRO (九州工大) ,  GONDO MASAYUKI (九州工大) ,  MIYAKE YOSUKE (九州工大) ,  KATO TAKAAKI (九州工大) ,  KAJIHARA SEIJI (九州工大)
Material： 電子情報通信学会技術研究報告(Web)  (IEICE Technical Report (Web))
Volume： 120  Issue： 288(DC2020 59-68)  Page： 1-6 (WEB ONLY)  Publication year： Dec. 04, 2020 
JST Material Number： U2030A  ISSN： 2432-6380  Document type： Proceedings
Article type： 短報  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： VLSI ,  *steepest descent method ,  delay ,  *delay characteristic ,  *forecast ,  degradation(alteration) ,  machine learning
Semi thesaurus term： VLSI ,  circuit delay ,  *gradient descent method ,  *degradation prediction

JST classification (2)： Measurement,testing and reliability of solid-state devices  (NC03040G) ,  Semiconductor integrated circuit  (NC03162T)

Reference (22)：

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Terms in the title (3)： 勾配降下法 ,  回路遅延 ,  劣化予測