Art

J-GLOBAL ID：202102284306022264   Reference number：21A0187666

Feasibility study of 650V rated FP-MOSFET

650V定格FP-MOSFET実現に向けた理論検討

Author (3)： HOSHIHARA KOKI (九州工大) ,  ITO ATSUSHI (九州工大) ,  OMURA ICHIRO (九州工大)
Material： 電気学会研究会資料
Issue： EDD-20-050-064/SPC-20-200-214 電子デバイス研究会/半導体電力変換研究会  Page： 47-50  Publication year： Dec. 21, 2020 
JST Material Number： Z0924B  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *MOSFET ,  *power transistor ,  semiconductor junction ,  CAD ,  process simulation ,  integral ,  ionization ,  model ,  structural design ,  feasibility ,  on resistance ,  dielectric strength
Semi thesaurus term： *power MOSFET ,  *field plate ,  super junction ,  TCAD ,  イオン化積分 ,  design model ,  高耐圧化

JST classification (1)： Transistors  (NC03070N)

Reference (12)：

• I. Yoshida, M. Kubo and S. Ochi, ′′A high power MOSFET with a vertical drain electrode and meshed gate structure,′′, Proc. IEDM, pp. 159-162, (1975).
• A. Nakagawa, J. Yoshida, T. Utagawa, T. Tsukakoshi, H. Tanabe and T. Kuramoto, ′′High voltage low on-resistance VDMOS FET,′′ Proceedings of the 13th Conference on Solid State Devices, 1981; Japanese Journal of Applied Physics, supplement 21-1, vol. 21, pp. 97-101, (1982).
• D. Ueda, H. Takagi and K. G., ′′A new vertical power MOSFET structure with extremely reduced on-resistance,′′ IEEE Transactions on Electron Devices, vol. 32, no. 1, pp. 2-6, (1985).
• Y. Baba, N. Matsuda, S. Yanagiya, S. Hiraki and S. Yasuda, ′′A study on a high blocking voltage UMOS-FET with a double gate structure,′′ Proc. the 4^th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 300-303, (1992).
• G. Deboy, N. Marz, J.-P. Stengl, H. Strack, J. Tihanyi and H. Weber, ′′A new generation of high voltage MOSFETs breaks the limit line of silicon,′′ Proc. IEDM Technical Digest, pp. 683-685, (1998).

Terms in the title (4)： 定格 ,  FP ,  MOSFET ,  理論