Design Technologies and Design Automation of Electronic Systems. A Formal Verification Method of Pipelined Microprocessors with Out-of-order Execution.

TAKENAKA TAKASHI; KITAMICHI JUNJI; TANIGUCHI KEN'ICHI

Art

J-GLOBAL ID：200902131014333478 Reference number：99A0378361

Design Technologies and Design Automation of Electronic Systems. A Formal Verification Method of Pipelined Microprocessors with Out-of-order Execution.

電子システムの設計技術と設計自動化あるクラスのOut-of-order型パイプラインCPUの設計の正しさの十分条件とその形式的検証

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Material：
Volume： 40 Issue： 4 Page： 1587-1596 Publication year： Apr. 15, 1999
JST Material Number： Z0778A ISSN： 0387-5806 Document type： Article
Article type：原著論文 Country of issue： Japan (JPN) Language： JAPANESE (JA)

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Digital computer systems in general , CAD,CAM

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