K. Tanaka, H. Yamaki, S. Miwa, H. Honda. Multi-Level Packet Processing Caches. The 2019 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22). 2019. 1-3
K. Tanaka, H. Yamaki, S. Miwa, H. Honda. Optimizing Memory Hierarchy within an Internet Router for High-Throughput and Energy-Efficient Packet Processing. ACM Student Research Competition (in conjunction with the 51st Annual ACM/IEEE International Symposium on Microarchitecture) (poster presentation). 2018. poster
Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda. Initial Study of Reconfigurable Neural Network Accelerators. 2016 FOURTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR). 2016. 707-709