K.M. Fant and S.A. Brandt, ”Null convention logictm: a complete and consistent logic for asynchronous digital circuit synthesis,” Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on, pp.261-273, 1996.
F. Menichelli, R. Menicocci, N. Olivieri, and A. Trifiletti, ”High-level side-channel attack modeling and simulation for security-critical systems on chips,” Dependable and Secure Computing, IEEE Transactions on, vol.5, no.3, pp.164-176, July 2008.
F. Burns, D. Shang, A. Koelmans, and A. Yakovlev, ”An asynchronous synthesis toolset using verilog,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol.1, pp.724-725 Vol.1, 2004.
R. Zhou, K.-S. Chong, B.-H. Gwee, and J.S. Chang, ”Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications,” Circuits and Systems (MWSCAS), 2011 IEEE 54th International Mid-west Symposium on, pp.1-4, 2011.
C.-F. Law, B.-H. Gwee, and J.S. Chang, ”Modeling and synthesis of asynchronous pipelines,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.19, no.4, pp.682-695, 2011.