Yoshinori Okajima, Adrian Cosoroaba, Hideo Kobayashi. An 0.18 μm embedded FCRAM ASIC with DRAM density and SRAM performance. February 2000ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International. 2000
July, VLSI Circuits, Digest of Technical Papers, Symposium. All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs. 1997
Yoshinori Okajima. Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Inteface. 1996
