Rchr
J-GLOBAL ID：200901048952981316
Update date: Feb. 01, 2024
Yanagisawa Masao
ヤナギサワ マサオ | Yanagisawa Masao
Affiliation and department：
Job title：
Professor
Homepage URL (2)：
http://www.islab.cs.waseda.ac.jp/
,
http://www.yanagi.cs.waseda.ac.jp/
Research field (3)：
Biological, health, and medical informatics
, Computer systems
, Control and systems engineering
Research keywords (1)：
Electron Devices and Apparatus Engineering,System Engineering,Computer Science, Bio-informatics,Computer-Aided Design
Research theme for competitive and other funds (16)：
- 2009 - 2011 Design Methods for Crypto LSI Implementations and Testing
- 2005 - 2007 Bioinformatics in silico by the Unification of Symobols and Patterns
- 2004 - 2006 Development of autonomous acoustic observation system using click sounds emitted by small cetacean and field experiments
- 2003 - 2005 Reconfigurable LSI Systems for Statistical Genetic Algorithms
- 2002 - 2004 Development of AUV for Whale following
- 1998 - 2000 An FPGA System for Digital Signal Processing and CAD tools
- 1996 - 1997 Development of Curriculums for Education of VLSI System Design.
- 1994 - 1995 Development of Educational Microprocessors for Computer Science Education
- 1992 - 1993 Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.
- 柔軟性の高いLSIレイアウト設計手法に関する研究
- 柔軟性の高いLSIレイアウト設計手法に関する研究
- 故障利用攻撃を検出できる耐タンパー暗号回路設計に関する研究
- ロバスト超低電圧回路設計技術に関する研究
- Synthesis tools for Adaptive Devices
- Genome Analysis
- SoC Design and CAD
Show all
Papers (506)：
-
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. A loop structure optimization targeting high-level synthesis of fast number theoretic transform. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2018. 2018-. 106-111
-
Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa. A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2018. E101A. 5. 831-843
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Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa. A hardware-Trojan classification method utilizing boundary net structures. 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. 2018. 2018-. 1-4
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Siya Bao, Masao Yanagisawa, Nozomu Togawa. Road-illuminance level inference across road networks based on Bayesian analysis. 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. 2018. 2018-. 1-6
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Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa. A low cost and high speed CSD-based symmetric transpose block FIR implementation. Proceedings of International Conference on ASIC. 2018. 2017-. 311-314
ｍore...
Books (1)：
-
最新VLSIの開発設計とCAD(共著)
ミマツデータシステム 1994
Lectures and oral presentations (36)：
-
Suspicious Timing Error prediction with In-Cycle Clock Gating
(2013)
-
Scan-Based Attack Against DES Cryptosystems Using Scan Signatures
(2012)
-
Weighted Adders with Selector Logics for Super-resolution and Its FPGA-based Evaluation
(2012)
-
State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Side Channel Attack on RSA Circuit
(2012)
-
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating
(2012)
ｍore...
Education (2)：
- - 1986 Waseda University Graduate School, Division of Science and Engineering
- - 1981 Waseda University Faculty of Science and Engineering
Professional career (1)：
Work history (5)：
- 1991 - 1998 Waseda University, Associate Professor
- 1998 - Waseda University, Professor
- 1994 - 1994 Passau University, Germany, Visiting Professor
- 1987 - 1991 Takushoku University, Associate Professor
- 1986 - 1987 University of California at Berkeley, Researcher
Awards (5)：
- 2011/03 - 電気通信普及財団賞
- 2008 - 海洋調査技術学会技術賞
- 1995 - Best Paper Award, Asia South Pacific Design Automation Conference
- 1990 - 安藤博記念学術奨励賞
- 1988 - 丹羽記念賞
Association Membership(s) (5)：
OR
, ACM:Association for Computing Machinery
, IEEE:The Institute of Electrical and Electronics Engineers,Inc.
, IPSJ
, IEICE
