Rchr
J-GLOBAL ID：201501085953163358
Update date: Feb. 01, 2024
Tawada Masashi
タワダ マサシ | Tawada Masashi
Affiliation and department：
Job title：
Junior Researcher(Assistant Professor)
Research theme for competitive and other funds (2)：
- 2020 - 2023 秘密情報の抜き取りに耐性を持つイジングモデル暗号化に関する研究
- 2016 - 2019 Write Reduction for Multi-level Cell Non-volatile Memory by Coding Optimally in the Worst Case
Papers (18)：
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Kojo Tatsuro, Tawada Masashi, Yanagisawa Masao, Togawa Nozomu. A-3-7 Worst-case Bit-Write-Reducing and Error-Correcting Code Generation by One-to-many Mapping for Non-Volatile Memories. Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference. 2015. 2015. 52-52
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KOJO Tatsuro, TAWADA Masashi, YANAGISAWA Masao, TOGAWA Nozomu. Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundamentals. 2015. 98. 12. 2484-2493
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TAWADA Masashi, KIMURA Shinji, YANAGISAWA Masao, TOGAWA Nozomu. ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundamentals. 2015. 98. 12. 2494-2504
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Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa. Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). 2015. 682-689
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TAWADA Masashi, KIMURA Shinji, YANAGISAWA Masao, TOGAWA Nozomu. Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories. Technical report of IEICE. VLD. 2014. 114. 328. 227-232
ｍore...
Patents (3)：
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処理装置、処理方法及び処理プログラム
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処理装置及び処理プログラム
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辞書検索方法、装置、およびプログラム
Professional career (1)：
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