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J-GLOBAL ID：202001003944567955   Update date: Sep. 17, 2024

Mori Takayuki

モリ タカユキ | Mori Takayuki
Affiliation and department：
Kanazawa Institute of Technology College of Engineering Department of Electrical and Electronic Engineering

About Kanazawa Institute of Technology College of Engineering Department of Electrical and Electronic Engineering


Job title： Assistant Professor
Research keywords  (4)： neuromorphic ,  energy harvesting ,  steep subthreshold slope ,  SOI
Research theme for competitive and other funds  (3)：
  • 2021 - 2026 A study on fan-in/fan-out augmentation of neuron circuits using a novel device
  • 2020 - 2021 Double Gate PN-Body Tied SOI-FETを用いた低消費電力ニューロン回路の研究開発
  • 2019 - 2020 新構造”PN-Body Tied SOI-FET”を用いた低消費電力ニューロン回路の研究開発
Papers (44)：
  • Masaki Kobayashi, Jiro Ida, Takayuki Mori. Neural Encoder Using “PN-Body Tied SOI-FET”. 2024 IEEE Silicon Nanoelectronics Workshop (SNW). 2024. 12. 107-108
  • Haruki Yonezaki, Takayuki Mori, Jiro Ida. Steep Slope Device “N-type Gate-Controlled Carrier-Injection SOI-Transistor”: Suppression of Hysteresis by Ar-ion Implantation and Possibility of CMOS. 2024 IEEE Silicon Nanoelectronics Workshop (SNW). 2024. 479. 57-58
  • Ryusei Ri, Takayuki Mori, Hiroshi Oka, Takahiro Mori, Jiro Ida. Back Bias Effect with Hysteresis in Cryogenic 200 nm SOI MOSFETs. 10th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2024. 2024
  • Hiroyoshi Matsushita, Takayuki Mori, Jiro Ida. Control of Hysteresis and Latch-Up on Steep Switching “PN-Body Tied SOI-FET Diode” by Ar-Ion Implantation. 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA). 2024
  • Haruki Yonezaki, Takayuki Mori, Jiro Ida. New Steep Subthreshold Slope Device “Gate-Controlled Carrier-Injection SOI-Transistor”. 2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM). 2024
ｍore...
MISC (25)：
  • 米崎 晴貴, 井田 次郎, 森 貴之, 石橋 孝一郎. 極低電圧動作を狙ったSteep SS "Dual-Gate型PN-Body Tied SOI-FET"試作結果-Evaluation of Steep Subthreshold Slope Device "Dual-Gate type PN-Body Tied SOI-FET" for Ultra Low Voltage Operation-情報センシング. 映像情報メディア学会技術報告 = ITE technical report. 2022. 46. 23. 19-22
  • 井田 次郎, 森 貴之. 招待講演 極低電力LSIに向けたSteep Slope "PN-Body Tied SOI-FET"の研究状況-Research Status of Steep Slope "PN-Body Tied SOI-FET" for Ultra low Power LSI Applications-情報センシング. 映像情報メディア学会技術報告 = ITE technical report. 2022. 46. 23. 15-18
  • Mori Takayuki, Ida Jiro. Neuron Circuit Using Dual Gate PN Body-Tied SOI-FET. JSAP Annual Meetings Extended Abstracts. 2021. 2021.1. 2346-2346
  • Ito Hiroki, Ida Jiro, Mori Takayuki. Analysis of Saturation Effect at Low Vds appearing in PN-Body Tied SOI-FET. JSAP Annual Meetings Extended Abstracts. 2020. 2020.2. 1839-1839
  • イシグロ ショウタ, イダ ジロウ, モリ タカユキ, イシバシ コウイチロウ. 急峻なSSを持つ"PN-Body Tied SOI-FET"のCMOSインバータ伝達特性. 2020. 44. 17. 57-60
ｍore...
Patents (1)：
Education (2)：
  • 2012 - 2014 Kanazawa Institute of Technology Graduate School of Engineering Graduate Program in Electrical Engineering and Electronics
  • 2010 - 2012 Kanazawa Institute of Technology College of Engineering Department of Electrical and Electronic Engineering
Professional career (1)：
  • Doctor of Engineering (Kanazawa Institute of Technology)
Work history (3)：
  • 2023/04 - 現在 Kanazawa Institute of Technology College of Engineering Department of Electrical and Electronic Engineering Assistant Professor
  • 2017/04 - 2023/03 Kanazawa Institute of Technology Center for Electric, Optic and Energy (EOE) Applications Researcher
  • 2014/04 - 2017/03 Toshiba Corporation Storage & Electronic Devices Solutions Company (Current Kioxia Corporation)
Committee career (1)：
  • 2020/11 - 現在 International Conference on Microelectronic Test Structures (ICMTS) Technical Program Committee
Association Membership(s) (3)：
IEEE ,  The Institute of Electronics, Information and Communication Engineers ,  The Japan Society of Applied Physics
※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

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