Art
J-GLOBAL ID：200902100483027938   Reference number：02A0326545

A Spacer Patterning Technology for Nanoscale CMOS.

ナノスケールCMOSのためのスペーサパターニング技術
Author (3)：
CHOI Y-K

About CHOI Y-K

(Univ. California, CA, USA)

About Univ. California, CA, USA

, 
KING T-J

About KING T-J

(Univ. California, CA, USA)

About Univ. California, CA, USA

, 
HU C

About HU C

(Univ. California, CA, USA)

About Univ. California, CA, USA


Material：
IEEE Transactions on Electron Devices  (IEEE Trans Electron Devices)

About IEEE Transactions on Electron Devices


Volume： 49  Issue： 3  Page： 436-441  Publication year： Mar. 2002 
JST Material Number： C0222A  ISSN： 0018-9383  CODEN： IETDAI  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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*MOSFET

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,...
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
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スペーサパターニング

About スペーサパターニング

,...
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JST classification (2)：
JST classification
Category name(code) classified by JST.
Transistors 
(NC03070N)

About Transistors

,  Manufacturing technology of solid-state devices 
(NC03030V)

About Manufacturing technology of solid-state devices

Terms in the title (2)：
Terms in the title
Keywords automatically extracted from the title.
ナノスケール

About ナノスケール

, 
CMOS

About CMOS


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