Art

J-GLOBAL ID：200902108495052203   Reference number：00A0559654

Fast Testable Design for SRAM-Based FPGAs.

SRAMベースFPGAの高速可試験設計

Author (3)： DOUMAR A (Chiba Univ., Chiba-shi, JPN) ,  OHMAMEUDA T (Chiba Univ., Chiba-shi, JPN) ,  ITO H (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E83-D  Issue： 5  Page： 1116-1127  Publication year： May. 25, 2000 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *FPGA ,...
Semi thesaurus term： データシフト

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JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (28)：

• STOROUD, C. BUILT-in self-test of logics blocks in FPGAs. 14th VLSI Test Symposium. 1996, 387-392
• STOROUD, C. Evaluation of FPGAs resources for BUILT-in self-test of programmable logic blocks. Proc. 1996 ACM/SIGDA International Symp. on FPGAs. 1996, 107-113
• STOROUD, C. Using ILA test for BIST in FPGAs. International Test Conference IEEE. 1996, 68-75
• STOROUD, C. BISTvased diagnostics of FPGAs logic blocks. International Test Conference. 1997, 447-539
• HUANG, W. K. Testing configurable LUT-based FPGA's. IEEE Trans. VLSI. 1998, 6, 2, 276-283

Terms in the title (4)： SRAM ,  FPGA ,  可試験 ,  設計