Art

J-GLOBAL ID：200902110892355861   Reference number：98A0139471

A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells.

機能的セルの最適レイアウト再生のための高速最小コストフローアルゴリズム

Author (4)： ARUNGSRISANGCHAI I (King Mongkut’s Inst. Technol., Bangkok, THA) ,  SHIGEHIRO Y (Osaka Univ., Suita-shi, JPN) ,  SHIRAKAW I (Osaka Univ., Suita-shi, JPN) ,  TAKAHASHI H (Okayama Prefectural Univ., Souja-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E80-A  Issue： 12  Page： 2589-2599  Publication year： Dec. 1997 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *LSI ,...

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JST classification (1)： General  (NC03161C)

Reference (25)：

• MURATA, H. Rectangle-packing-based modular placement. Proc. IEEE International Conference on Computer-Aided Design. 1995, 472-479
• ESBENSEN, H. Exploring the design space for building-block placements considering area, space, aspect ratio, path delays and routing congestion. Proc. ACM/SIGDA Physical Design Workshop. 1996, 126-133
• SHIGEHIRO, Y. Automatic layout recycling based on layout description and linear programming. IEEE Trans. Comput.-Aided Des. Integrates Circuits & Syst. 1996, 15, 8, 959-967
• HSUEH, M. Y. Symbolic layout and compaction of integrated circuits. ERL Memo. 1979
• IRI, M. Network Flow, Transportation and Scheduling. 1969

Terms in the title (2)： セル ,  レイアウト