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J-GLOBAL ID:200902120636709961   Reference number:01A0078943

Design of a Parallel VLSI Processor for Road Extraction Based on Logic-in-Memory Architecture.

ロジックインメモリアーキテクチャに基づく道路抽出用VLSIプロセツサの構成
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Volume: 36  Issue: 11  Page: 1009-1017  Publication year: Nov. 30, 2000 
JST Material Number: S0104A  ISSN: 0453-4654  CODEN: KJSRA  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Special-purpose arithmetic and control units  ,  Electric equipment 
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