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J-GLOBAL ID：200902129074767278
Reference number：00A0262814
Low-Power High-Speed CMOS LSI Technologies. A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection.
推論方法選択を用いた高性能低電力キャッシュアーキテクチャ
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Author (3)：
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Material：
Volume：
E83-C
Issue：
2
Page：
186-194
Publication year：
Feb. 25, 2000
JST Material Number：
L1370A
ISSN：
0916-8524
Document type：
Article
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
ENGLISH (EN)
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JST classification (1)：
JST classification
Category name(code) classified by JST.
Semiconductor integrated circuit
Reference (18)：
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BAHAR, R. I. Power and performance tradeoffs using various caching strategies. Proc. 1998 International Symposium on Low Power Electronics and Design. 1998, 64-69
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BRAD, C. Predictive sequential associative cache. Proc. 2nd International Synposium on High-Performance Computer Architecture. 1996, 244-253
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CHANG, J. H. Cache design of a sub-micron CMOS system370. Proc. 14th International Symposium on Computer Architecture. 1987, 208-213
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GHOSE, K. Energy efficient cache organizations for superscalar processors. Power-Driven Microarchitecture Workshop In Conjunction With ISCA98 in Barcelona. 1998
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HAJI, N. B. I. Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. Proc. 1998 International Symposium on Low Power Electronics and Design. 1998, 70-75
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