Electrical Model of the Floating Gate Defect in CMOS IC’s: Implications on I<sub>DDQ</sub> Testing.

CHAMPAC V H; RUBIO A; FIGUERAS J

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J-GLOBAL ID：200902178221023175 Reference number：94A0342957

Electrical Model of the Floating Gate Defect in CMOS IC’s: Implications on I_DDQ Testing.

CMOSICにおけるフローティングゲート欠陥の電気的モデル I_DDQテストとの関係

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Volume： 13 Issue： 3 Page： 359-369 Publication year： Mar. 1994
JST Material Number： B0142C ISSN： 0278-0070 CODEN： ITCSDI Document type： Article
Article type：原著論文 Country of issue： United States (USA) Language： ENGLISH (EN)

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Measurement,testing and reliability of solid-state devices

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Electrical Model of the Floating Gate Defect in CMOS IC’s: Implications on IDDQ Testing.

Electrical Model of the Floating Gate Defect in CMOS IC’s: Implications on I_DDQ Testing.