Art

J-GLOBAL ID：200902183212554544   Reference number：96A0681763

Parallel Processing. Ordered Multithreaded-Execution Model: The Proposal and Evaluation.

並列処理 順序付きマルチスレッド実行モデルの提案とその評価

Author (4)： MOTOMURA MASATO (NEC マイクロエレクトロニクス研) ,  INOUE TOSHIAKI (NEC マイクロエレクトロニクス研) ,  TORII SUNAO (日本電気 C&C研) ,  KONAGAYA AKIHIKO (日本電気 C&C研)
Material： 情報処理学会論文誌  (IPSJ Journal)
Volume： 37  Issue： 7  Page： 1355-1366  Publication year： Jul. 1996 
JST Material Number： Z0778A  ISSN： 0387-5806  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： parallel computer ,...

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JST classification (1)： Control systems  (JC02030K)

Reference (9)：

• WALL, D. W. Limits of Instruction-Level Parallelism. Proc. Fourth International Conference on Architectural Support for Programming Languages and Operating Systems. 1991, 176-188
• LAM, M. S. Limits of Control Flow on Parallelism. Proc. 19th Annual International Symposium on Computer Architecture. 1992, 46-57
• SAKAI, S. An Architecture of a Dataflow Single Chip Processor. Proc. 16th Annual International Symposium on Computer Architecture. 1989, 46-53
• NIKHIL, R. S. A Multithreaded Massively Parallel Architecture. Proc. 19th Annual International Symposium on Computer Architecture. 1992, 156-167
• AGARWAL, A. April: A Processor Architecture for Multiprocessing. Proc. 17th Annual International Symposium on Computer Architecture. 1990, 104-114

Terms in the title (6)： 並列処理 ,  順序 ,  マルチスレッド ,  モデル ,  提案 ,  評価