Ultrathin(<4nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits.

GREEN M L; GUSEV E P; DEGRAEVE R; GARFUNKEL E L

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J-GLOBAL ID：200902183617757442 Reference number：01A0912519

Ultrathin(<4nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits.

シリコンマイクロエレクトロニクス用の超薄(<4nm)SiO2およびSi-O-Nゲート誘電体層プロセシング,構造,物理的および電気的限界

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Author (4)： , , ,
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Volume： 90 Issue： 5 Page： 2057-2121 Publication year： Sep. 01, 2001
JST Material Number： C0266A ISSN： 0021-8979 CODEN： JAPIAU Document type： Article
Article type：文献レビュー Country of issue： United States (USA) Language： ENGLISH (EN)

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Oxide thin films , Metal-insulator-semiconductor structures , Manufacturing technology of solid-state devices

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Ultrathin(<4nm) SiO<sub>2</sub> and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits.